| ON THE CORRUPTING
INFLUENCE OF VARIABILITY IN SEMICONDUCTOR MANUFACTURING
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|---|---|---|
| Alexander K.
Schoemig Infineon Technologies AG Operational Excellence P.O. Box 10 09 44 D-93009 Regensburg, GERMANY |
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| ABSTRACT | ||
| This paper describes two simulation experiments using a model of a real medium sized multi-product semiconductor chip fabrication facility. The results presented clearly show the corrupting influence of variability, in this case caused by machine and tool unavailability. The immediate conclusion out of the results is that reducing the inherent variability of a manufacturing system improves the overall system performance. Hence, sampling shop-floor data should not only include first order statistics, but also measures that allow to monitor and model the variability of the machinery. | ||
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| VALIDATING SIMULATION
MODEL CYCLE TIMES AT SEAGATE TECHNOLOGY |
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|---|---|---|
| Navdeep S.
Grewal Alvin C. Bruska Timbur M. Wulf Wafer Systems Engineering Seagate Technology One Disc Drive Bloomington, MN 55435, U.S.A. |
Jennifer K.
Robinson Chance & Robinson, Inc. 7171 Buffalo Speedway, #639 Houston, TX 77025, U.S.A. | |
| ABSTRACT | ||
| This paper describes the validation of cycle times in a factory simulation model of a new Recording Head Wafer manufacturing facility at Seagate Technology, Minneapolis, MN. The project goals were to determine which factors were causing cycle time deltas between the model and the actual factory, and to add detail to the simulation model to bring cycle times closer to reality. The study found that the most significant contributors to the cycle time delta were number of tools, number of operators, level of operator cross-training, and assumptions about rework, downtime, and equipment dedication. | ||
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| CONLOAD -- A NEW LOT
RELEASE RULE FOR SEMICONDUCTOR WAFER FABS
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|---|---|---|
| Oliver
Rose Institute of Computer Science University of Wurzburg 97074 Wurzburg, GERMANY |
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| ABSTRACT | ||
| In this paper, we present CONLOAD, a new lot release rule for wafer fabs. It was developed to overcome some performance problems of traditional lot release rules like CONWIP or Workload Regulation during product mix changes. We show that CONLOAD outperforms CONWIP and Workload Regulation with respect to keeping the bottleneck utilization at a desired level and to provide a smooth evolution of the WIP. | ||
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| Assessment of Potential
Gains in Productivity Due to Proactive Reticle Management Using Discrete
Event Simulation |
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|---|---|---|
| Sungmin
Park Arizona State University Tempe, Arizona |
John Fowler
Ph.D. Arizona State University Tempe, Arizona | |
| Matt Hickie Motorola MOS 12 Chandler, Arizona |
Matt Carlyle Ph.D. Arizona State University Tempe, Arizona | |
| ABSTRACT | ||
| Photolithography is often the constraining equipment in semiconductor wafer fabrication plants due to the number of times the product must process through it. Modern day photolithography is performed on a cluster tool that is a combination of a stepper and track. It is obvious that the combined availability of the cluster tool is critical to throughput, but what is not so obvious is the throughput restriction from a secondary constraint known as a reticle. Every layer of a product needs a unique reticle for processing. Setup issues arising from the requirement of reticles affects productivity of photolithography and the entire wafer fabrication line if photolithography is the bottleneck. Efficient management of reticles (with regard to setup and storage on a stepper) based on current system status provides a strategic and tactical advantage. In this paper, a SLAM discrete event simulation model is to mimic the setup and storage of reticles. This enables the collection of information that can used to identify potential gains in tactical reticle management. The simulation model will be explained in detail along with output results for the tactical issues. The relationship between the simulation and the network flow model for proactive reticle management will also be discussed. | ||
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| OPERATIONAL SIMULATION
OF AN X-RAY LITHOGRAPHY CELL: COMPARISON OF 200MM AND 300MM WAFERS
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|---|---|---|
| K. Preston White,
Jr. Department of Systems Engineering University of Virginia Institute for Microelectronics University of Virginia Charlottesville, VA 22903-2442 |
Walter J. Trybula
International SEMATECH, Inc. 2706 Montopolis Drive Austin, TX 78741-6499 | |
| ABSTRACT | ||
| We review progress on a project to evaluate prospective operations in a semiconductor wafer fab that employs next-generation, proximity X-ray lithography to pattern the critical dimensions of computer chips. A simulation model is developed that captures the processing of wafers through an X-ray lithography cell using a synchrotron as the source of exposure radiation. The model incorporates the best current information on unit-cell design and processing times and implements a range of events that interrupt the flow of wafers processing on the cell. Performance measures estimated from the simulation include the weekly throughput for the cell and the frequency of SEMI E-10 equipment states for the corresponding exposure tool. Simulation experiments are conducted to compare the performance of a cell fabricating 200mm wafers with that of a cell fabricating 300mm wafers, for each of three different chip sizes. Results illustrate the anticipated dependence of average wafer throughput on wafer size and assumptions regarding the number of chips per wafer, with a maximum of approximately 3400 wafers/week for 200mm wafers with 25x25mm field size. Ignoring wafer-sort losses, however, a maximum throughput of approximately 410,000 chips/week is realized for 300mm wafers with 11x22mm fields. Remarkably, the distribution of equipment states remains relatively unchanged across simulation experiments. | ||
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| USING SIMULATION AND
GENETIC ALGORITHMS TO IMPROVE CLUSTER TOOL PERFORMANCE
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|---|---|---|
| Mathias A.
Dummler Institute of Computer Science University of Wurzburg Am Hubland, 97074 Wurzburg, GERMANY |
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| ABSTRACT | ||
| In this paper, we present an approach to generate optimal processing sequences of lots at cluster tools. We consider the problem of sequencing lots, where each lot can be processed by any of available cluster tools. The proposed method combines simulation and a genetic algorithm to generate lot processing sequences. We show that our approach leads to a significant reduction of cycle times at cluster tools. | ||
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| CAPACITY PLANNING FOR
SEMICONDUCTOR WAFER FABRICATION WITH TIME CONSTRAINTS BETWEEN OPERATIONS
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|---|---|---|
| Jennifer
Robinson Chance & Robinson, Inc. 7171 Buffalo Speedway #639 Houston, TX 77025, U.S.A. |
Richard
Giglio The University of Massachusetts at Amherst Department of Mechanical and Industrial Engineering Amherst, MA 01002, U.S.A. | |
| ABSTRACT | ||
| Planning capacity for wafer fabrication is complicated by time constraints between process steps. For example, if certain baking operations are not started within two hours of a prior cleaning then the lot in question must be sent back to be cleaned again. For two-element systems an approximation based on M/M/c queuing formulas is developed and compared with results from discrete event simulations. The approximation performs well in predicting the probability of reprocessing and provides a bound that can easily be included in the spreadsheet capacity models often employed by manufacturers. For multi-element systems, the results of a fluid model used to understand general system characteristics are summarized. Discrete event simulation was used to validate the results of the analytic models and provide guidelines for operating time-constrained systems. | ||
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| CRITICALITY OF DETAILED
MODELING IN SEMICONDUCTOR SUPPLY CHAIN SIMULATION
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|---|---|---|
| Sanjay
Jain Chu-Cheow Lim Boon-Ping Gan Yoke-Hean Low Gintic Institute of Manufacturing Technology 71 Nanyang Drive SINGAPORE 638075 |
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| ABSTRACT | ||
| Supply chain management offers a large potential for organizations to reduce costs and improve customer service performance. Simulation of supply chains can help in these objectives by evaluating the impact of alternate inventory control policies. Supply chain simulation involves modeling of multiple factories across the chain and can get quite complex. Analysts typically carry out such simulation at a coarse level of detail to keep the complexity and computing resources manageable. However, modeling at coarse levels may reduce the accuracy of outputs and affect the quality of decisions. In this paper, we report on a study to compare the quality of results at different levels of details in a semiconductor supply chain simulation. | ||
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| MACHINE
DEDICATION UNDER PRODUCT AND PROCESS DIVERSITY |
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|---|---|---|
| Darius
Rohan IBM Corporation |
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| ABSTRACT | ||
| Increased product and process diversity
in semiconductor manufacturing line has confronted the operations managers
with the challenge of managing the setups that usually accompany changes
of processes or products at a machine. Recall that under a flexible
manufacturing regime, a setup is employed prior to processing in order to
prepare the machine with the specific recipe required by the job at hand.
Such a setup is performed only if the job last processed by the machine
utilized a different recipe. One way to curtail setups is to divide like machines into groups and dedicate each group of machines to one (or a small number) of recipes. These machine-to-recipe dedications are aimed to eliminate (or reduce) the setups and hence improve productivity. However, these dedications also result in reduced flexibility at operation time and hence serve as a detractor to productivity. To investigate this trade off and evaluate the net effect on productivity, an analytical tool was developed at IBM Microelectronics. In our first set of experiments we confined ourselves to the cases where the number of recipes were equal to the number of machines at the workstation under study. We found that the aforementioned trade off depends largely on two factors: ratio of setup duration to processing duration, and the scheduling policy (Rohan, Proceedings of the 1999 Western MultiConference).. This elucidated that the dedication decisions should be independent of the absolute values of setup duration or process duration. Our experiments also indicated that the corresponding break-even points were fairly insensitive to the number of recipes (or machines). In this paper we will relax our assumption regarding recipe to machine equality. | ||
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| MODELING LOT ROUTING
SOFTWARE THROUGH DISCRETE-EVENT SIMULATION
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|---|---|---|
| Chad D.
DeJong Thomas Jefferson Intel Corporation 5000 West Chandler Boulevard, Mail Stop CH3-84 Chandler, Arizona 85226, U.S.A. |
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| ABSTRACT | ||
| Intel has recently developed lot routing
tools that can theoretically minimize local and overall lot movement.
These developments were required to maximize the flexibility of existing
AMHS and minimize the time needed to retrieve lots for
processing. In order to gain insight of how these lot routing rules impact manufacturing, and how they should be configured, Intel uses two different analysis tools. A static spreadsheet model was used to determine the impact of the new lot routing rules in terms of AMHS lot movement volume. The second level of analysis was to use dynamic discrete-event simulation to determine the impact to AMHS and equipment utilization. Both methods were used to determine how tool policy rules should be set for each operation in the process flow, and minimize impact to AMHS and enhance performance, while meeting manufacturing requirements. The static model analysis showed that ideal use of the lot routing algorithm had a very significant impact on AMHS transport requirements. The dynamic discrete-event modeling showed that the lot routing policies can be modified to enhance system performance. These modifications resulted in key learnings about configuring the lot routing software. | ||
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| A MODEL OF A 300MM WAFER
FABRICATION LINE |
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|---|---|---|
| Philip L.
Campbell Darius Rohan IBM Microelectronics Division East Fishkill, NY 12533, U.S.A. |
Edward A.
MacNair IBM T.J. Watson Research Center Yorktown Heights, NY 10598, U.S.A. | |
| ABSTRACT | ||
| Semiconductor factories are very expensive to build and operate. It is critical to understand how to design and operate them efficiently. We describe a simulation model of a planned 300mm wafer fabrication line that we are using to make strategic decisions related to the factory. | ||
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| APPLICATION OF
SIMULATION AND THE BOEHM SPIRAL MODEL TO 300-MM LOGISTICS SYSTEM RISK
REDUCTION |
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|---|---|---|
| Theron Colvin Jerry Weckman PRI Automation Automation Planning and Design 1250 S. Clearview Ave. Mesa, Arizona 85208, USA |
Robert J.
Gaskins PRI automation 805 Middlesex Turnpike Billerica, Massachusetts 01821-3986, USA |
Gerald T. Mackulak,
Ph.D. Industrial Engineering Arizona State University Tempe, Arizona 85287-5906, USA |
| ABSTRACT | ||
| Building on the lessons learned from the
150-mm-to 200-mm transition in semiconductor manufacturing, much work has
gone into the planning and development of 300-mm fabs. Examples of this
include the work produced by SEMI, International SEMATECH's I300I and
Japan's J300 programs. This work includes various standards and guidelines
regarding the architecture and interfaces of loadports, equipment and
software components. However, despite these efforts, there are a number of significant 300-mm risks that remain. Some of these risks involve specific fab operational methodologies, which may vary depending upon the type of fab involved. Additionally, there are many other risks associated with the development and implementation of a robust 300-mm logistics system. The purpose of this paper is to:
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