WSC 2006 Abstracts

Semiconductor Manufacturing Track

Tuesday 8:30:00 AM 10:00:00 AM
Factory Simulation

Chair: Lars Mönch (University of Hagen)

Estimating Expected Completion Times with Probabilistic Job Routing
Nirmal Govind (Intel Corporation) and Theresa M Roeder (San Francisco State University)

A common problem in production environments is the need to estimate the remaining time in system for work-in-progress jobs. Simulation can be used to obtain the estimates. However, when the future path of a job is uncertain (due to stochastic events such as rework), using simulation to estimate the remaining cycle time of a job at step k can be imprecise; traditional confidence intervals on the estimated remaining cycle times may be too large to be of practical significance. We propose a response surface methodology-based approach to estimating conditional confidence intervals on the remaining cycle times as jobs progress through the system and more information is obtained on them. This method will provide more useful and accurate estimates of remaining cycle times at various stages of the process flow. Further, we outline two different simulation approaches for estimating the response surfaces used to generate the confidence intervals.

Modeling Semiconductor Tools for Small Lotsize Fab Simulations
Kilian Schmidt (Advanced Micro Devices), Oliver Rose (Dresden University of Technology) and Joerg Weigang (Advanced Micro Devices)

Short cycle times are critical to the success of semiconductor manufacturing. The addition of more and more mask layers leads to higher raw process times and makes short cycle times an increasingly challenging task. One cycle time reduction possibility semiconductor manufacturers now look at is lotsize reduction. A reduction in lotsize transfers directly into lower raw process times. Modeling and simulation are key to assess opportunities and risks of such an approach. This paper looks at the implications that follow from small lotsizes for tool models used for the assessment.

Economy of Scale Effects for Larger Wafer Fabs
Oliver Rose (Dresden University of Technology)

In this paper, we present the results of a simulation study for semiconductor wafer fabrication facilities (wafer fabs) where we multiplied the number of tools per tool group and the number of operators. We were interested in the effects on the product cycle times when we keep the fab utilization constant while increasing the size of the tool groups by constant factors, i.e., forming so-called giga fabs. It turns out, that the drop in cycle time is considerable.

Tuesday 10:30:00 AM 12:00:00 PM
Performance Analysis in Semiconductor Manfacturing

Chair: John Fowler (Arizona State University)

Simulation Analysis on the Impact of Furnace Batch Size Increase in a Deposition Loop
Boon Ping Gan and Peter Lendermann (Singapore Institute of Manufacturing Technology) and Kelvin Paht Te Quek, Bart van der Heijden, Chen Chong Chin, and Choon Yap Koh (Systems on Silicon Manufacturing Co. Pte. Ltd.)

In the dynamic environment of semiconductor manufacturing operations, a bottleneck could be created at the bake furnaces of the deposition loop as capacity expands. Upgrading of the bake furnaces by adding a lot-per-batch in the boat or purchasing a new furnace are two possible solutions to this problem. A simulation model was constructed to assist the decision making, with the behavior of the wet benches (upstream tools) and cluster tools (downstream tools) being modeled in detail. We concluded that a limited number of furnaces upgrade is sufficient to sustain the capacity expansion. But the bottleneck was shifted to an upstream tool, which required the backup tool to be activated to manage the queue. A loading policy that constrains batches to queue at maximum time before loading into the furnaces has to be implemented to balance the efficiency at the furnaces and their downstream tools, without compromising on the cycle time.

Indirect Cycle-Time Quantile Estimation for Non-FIFO Dispatching Policies
Jennifer M. Bekki and Gerald T Mackulak (Arizona State University) and John W Fowler (Arizona State Ubiversity)

Previous work has shown that the Cornish-Fisher expansion (CFE) can be used successfully in conjunction with discrete event simulation models of manufacturing systems to estimate cycle-time quantiles. However, the accuracy of the approach degrades when non-FIFO dispatching rules are employed for at least one workstation. This paper suggests a modification to the CFE-only approach which utilizes a power data transformation in conjunction with the CFE. An overview of the suggested approach is given, and results of the implemented approach are presented for a model of a non-volatile memory factory. Cycle-time quantiles for this system are estimated using the CFE with and without the data transformation, and results show a significant accuracy improvement in cycle-time quantile estimation when the transformation is used. Additionally, the technique is shown to be easy to implement, to require very low data storage, and to allow easy estimation of the entire cycle-time cumulative distribution function.

A Full Factory Transient Simulation Model for the Analysis of Expected Performance in a Transition Period
Moti Klein and Adar Kalir (Intel)

Intel’s Fab-18 is based in Israel, and has transitioned from producing 0.18-micron logic devices to producing 90nM flash products. During this transition period, the factory has de-ramped in volume of logic while ramping-up flash. AutoSched AP software was utilized for the development of a transient simulation model of the Fab’s behavior during this period. It is the first attempt, at Intel, to utilize a full factory simulation in order to analyze and support decisions that pertain to a transient period of parallel de-ramp and ramp-up of technologies. Unlike typical simulation models for the analysis of factory performance and behavior in steady-state, the transient model poses several modeling challenges and requires major adjustments in dealing with these challenges. In this paper, we discuss those aspects. The benefits and contribution of such a model to decision making and the improvement of factory performance are also presented.

Tuesday 1:30:00 PM 3:00:00 PM
Dispatching and Scheduling Approaches

Chair: Daniel Quadt (Infineon Technologies AG)

The Use of Slow Down Factors for the Analysis and Development of Scheduling Algorithms for Parallel Cluster Tools
Robert Unbehaun and Oliver Rose (Dresden University of Technology)

In this paper, we describe the problem of developing scheduling algorithms for an environment of parallel cluster tools, which is a special case of the parallel unrelated machines problem. At first we will describe the problem under consideration in detail and then present our scheduling environment and the idea of using slow down factors to predict lot cycle times to evaluate schedules and parts of them. This article is more a conceptual kind of work containing mostly basic thoughts to illustrate facets of the problem and first solution ideas. Nonetheless the authors see a high potential in examining these questions. Little research has been done on that issue so far.

Simulation-Based Selection of Machine Criticality Measures for a Shifting Bottleneck Heuristic
Jens Zimmermann and Lars Moench (FernUniversitaet in Hagen)

In this paper, we investigate the influence of several machine criticality measures on the performance of a shifting bottleneck heuristic for complex job shops. The shifting bottleneck heuristic is a decomposition approach that tackles the overall scheduling problem by solving a sequence of tool group scheduling problems and compose the overall solution by using a disjunctive graph. Machine criticality measures are responsible for the sequence of the considered tool group scheduling problems. We suggest a new machine criticality measure that is a weighted sum of several existing criticality measures. It turns out that the shifting bottleneck heuristic performs well compared to dispatching rules when the suggested criticality measure is used. We present the results of computational experiments.

Tuesday 3:30:00 PM 5:00:00 PM
Planning Approaches in Semiconductor Manfacturing

Chair: Oliver Rose (Dresden University of Technology)

Using System Dynamics Simulations to Compare Capacity Models for Production Planning
Seza Orcun and Reha Uzsoy (Purdue University) and Karl Kempf (Intel Corporation)

While a variety of optimization formulations of production planning problems have been proposed over the last fifty years, the majority of these are based on simple models of capacity that fail to reflect the nonlinear relationship between workload and lead times induced by the queuing behavior of capacitated production resources. We use system dynamics simulations of a simple capacitated production system to examine the performance of several different capacity models that yield load-dependent lead times, and relate these models to those used in system dynamics models of production systems.

Flexible Experimentation and Analysis for Hybrid DEVS and MPC Models
Dongping Huang, Hessam S. Sarjoughian, Daniel E. Rivera, and Gary W. Godding (Arizona State University) and Karl G. Kempf (Intel Corporation)

Discrete-event simulation and control-theoretic approaches lend themselves to studying semiconductor manufacturing supply-chain systems. In this work, we detail a modeling approach for semiconductor manufacturing supply-chain systems in a hybrid DEVS/MPC testbed that supports experimentations for DEVS and MPC models using DEVS/MPC KIB. This testbed supports detailed analysis and design of interactions between discrete processes and tactical controller. A set of experiments have been devised to illustrate the role of modeling interactions between Discrete Event System Specification and Model Predictive Control models. The testbed offers novel features to methodically identify and analyze complex model interactions and thus support alternative designs based on tradeoffs between model resolutions and execution times.

An Analytical Model of Vehicle-Based Automated Material Handling Systems in Semiconductor Fabs
Dima Nazzal (University of Central Florida) and Leon F. McGinnis (Georgia Institute of Technology)

This research explores analytical models useful in the design of vehicle-based Automated Material Handling Systems (AMHS) to support semiconductor manufacturing. The objective is to correctly estimate the throughput and move request delay. This analysis proposes a computationally effective analytical approach to multi-vehicle AMHS performance modeling for a simple closed loop. A probabilistic model is developed, based on a detailed description of AMHS operations, and the system is analyzed as an extended Markov chain. The model tracks the operations of one vehicle on the closed-loop considering the possibility of vehicle-blocking. This analysis provides the essential parameters such as the blocking probabilities in order to estimate the performance measures. A numerical example is analyzed and simulated using Automod to demonstrate and validate the queuing model.

Wednesday 8:30:00 AM 10:00:00 AM
Modeling Approaches for Wafer Fabs

Chair: Leon McGinnis (Georgia Institute of Technology)

Systems Engineering and Design of High Tech Factories
Leon McGinnis, Edward Huang, and Kan Wu (Georgia Institute of Technology)

Contemporary technology for Product Lifecycle Management (PLM) integrates computer aided design (CAD) and engineering analysis (CAE) to support rapid, distributed, team-oriented product data development and management, including high fidelity simulation on demand. This technology potentially provides a platform for creating a new generation of factory design tools which enable “on demand” simulation and analytic model results to be used by factory designers. This paper describes the opportunity, and provides an illustration in the context of semiconductor wafer fab design.

Simulation-Based Scheduling of Parallel Wire-Bonders with Limited Clamp&Paddles
Daniel Quadt (Infineon Technologies AG)

We present a scheduling procedure for the wire-bonding operation of a semiconductor assembly facility. The wire-bonding operation typically consists of a large number of unrelated parallel machines and is typically one of the bottlenecks in an assembly facility. The scheduling procedure is able to handle setup times, limited fixtures (clamp&paddles) and non-zero machine ready-times (initial work in progress). It is based on a simulator that generates a schedule and a Simulated Annealing approach to optimize the schedule. Some preliminary results from an implementation in a large assembly facility are given.

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